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a ad7650 * rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 16-bit, 570 ksps low cost cmos adc functional block diagram switched cap dac 16 control logic and calibration circuitry clock ad7650 data[15:0] busy rd cs ser/ par ob/ 2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in+ in pd reset serial port parallel interface cnvst warp impulse features throughput 570 ksps (warp mode) 500 ksps (normal mode) 16 bits resolution analog input voltage range: 0 v to 2.5 v no pipeline delay parallel and serial 5 v/3 v interface spi ?/ qspi ?/ microwire ?/ dsp compatible single 5 v supply operation power dissipation 77 mw typical @ 444 ksps (impulse mode) 21 w @ 100 sps power-down mode: 7 w max package: 48-lead quad flat pack (lqfp) or 48-lead frame chip-scale pack (lfcsp) pin-to-pin compatible with pulsar adcs applications data acquisition instrumentation digital signal processing spectrum analysis medical instruments battery-powered systems process control general description the ad7650 is a 16-bit, 570 ksps, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. the part contains a high-speed 16-bit sampling adc, an internal conversion clock, error correction circuits, and both serial and parallel system interface ports. it features a very high sampling rate mode (warp) and, for asynchronous conversion rate applications, a fast mode (normal) and, for low power applications, a reduced power mode (impulse) where the power is scaled with the throughput. it is fabricated using analog devices high-performance, 0.6 micron cmos process and is available in a 48-lead lqfp or in a tiny 48-lead chip scale package with operation specified from C40 c to +85 c. product highlights 1. fast throughput the ad7650 is a 570 ksps, charge redistribution, 16-bit sar adc. 2. single-supply operation the ad7650 operates from a single 5 v supply. in im pulse mode, its power dissipation decreases with the throughput from 77 mw at 444 ksps throughput to, for in stance, only 21 w at a 100 sps throughput. it consumes 7 w maximum when in power-down. 3. serial or parallel interface versatile parallel or 2-wire serial interface arrangement com- patible with both 3 v or 5 v logic. * patent pending. spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation.
rev. 0 ad7650?pecifications (?0 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) C2C parameter condition min typ max unit resolution 16 bits analog input voltage range v in+ C v inC 0v ref v operating input voltage v in+ C0.1 +3 v v inC C0.1 +0.5 v analog input cmrr f in = 10 khz 62 db input current 570 ksps throughput 7 a input impedance see analog input section throughput speed complete cycle in warp mode 1.75 s throughput rate in warp mode 1 570 ksps time between conversions in warp mode 1 ms complete cycle in normal mode 2 s throughput rate in normal mode 0 500 ksps complete cycle in impulse mode 2.25 s throughput rate in impulse mode 0 444 ksps dc accuracy integral linearity error C6 +6 lsb 1 no missing codes 15 bits transition noise 0.7 lsb full-scale error 2 ref = 2.5 v 0.12 % of fsr unipolar zero error 2 5 25 lsb 3 power supply sensitivity avdd = 5 v 5% 3 lsb ac accuracy signal-to-noise f in = 100 khz 86 db 4 spurious free dynamic range f in = 100 khz 98 db total harmonic distortion f in = 45 khz C98 db f in = 100 khz C96 db signal-to-(noise + distortion) f in = 100 khz 86 db C60 db input, f in = 100 khz 30 db C3 db input bandwidth 18 mhz sampling dynamics aperture delay 2 ns aperture jitter 5 ps rms transient response full-scale step 250 ns reference external reference voltage range 2.3 2.5 avdd C 1.85 v external reference current drain 570 ksps throughput 115 a digital inputs logic levels v il C0.3 +0.8 v v ih 2.0 ovdd + 0.3 v i il C1 +1 a i ih C1 +1 a digital outputs data format parallel or serial 16-bit pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = C500 a ovdd C 0.6 v power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v
rev. 0 C3C ad7650 timing specifications parameter symbol min typ max unit refer to figures 8 and 9 convert pulsewidth t 1 5ns time between conversions t 2 1.75/2/2.25 note 1 s (warp mode/normal mode/impulse mode) cnvst low to busy high delay t 3 30 ns busy high all modes except in t 4 1.5/1.75/2 s master serial read after convert mode (warp mode/normal mode/impulse mode) aperture delay t 5 2ns end of conversion to busy low delay t 6 10 ns conversion time t 7 1.5/1.75/2 s (warp mode/normal mode/impulse mode) acquisition time t 8 250 ns reset pulsewidth t 9 10 ns refer to figures 10, 11 and 12 (parallel interface modes) cnvst low to data valid delay t 10 1.5/1.75/2 s (warp mode/normal mode/impulse mode) data valid to busy low delay t 11 45 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 515ns refer to figures 13 and 14 (master serial interface modes) 2 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay 2 t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay t 17 25/275/525 ns (warp mode/normal mode/impulse mode) sync asserted to sclk first edge delay t 18 4ns internal sclk period t 19 40 75 ns internal sclk high (invsclk low) 3 t 20 30 ns internal sclk low (invsclk low) 3 t 21 9.5 ns sdout valid setup time t 22 4.5 ns sdout valid hold time t 23 3ns parameter condition min typ max unit power supplies (continued) operating current 5 570 ksps throughput avdd 15.5 ma dvdd 6 4.2 ma ovdd 6 100 a power dissipation 6 570 ksps throughput 5 115 mw 444 ksps throughput 7 77 mw 100 sps throughput 7 21 w in power-down mode 8 7 w temperature range 9 specified performance t min to t max C40 +85 c notes 1 lsb means least significant bit. with the 0 v to 2.5 v input range, one lsb is 38.15 v. 2 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 3 tested in warp mode. 4 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale unless o therwise specified. 5 in warp mode. 6 tested in parallel reading mode. 7 in impulse mode. 8 with all digital inputs forced to ovdd or ognd respectively. 9 contact factory for extended temperature range. specifications subject to change without notice. ( 40 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) rev. 0 C3C ad7650
rev. 0 ad7650 C4C timing specifications parameter symbol min typ max unit refer to figures 13 and 14 (continued) sclk last edge to sync delay t 24 3 cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert t 28 2.75/3/3.25 s (warp mode/normal mode/impulse mode) cnvst low to sync asserted delay t 29 1/1.25/1.5 s (warp mode/normal mode/impulse mode) sync deasserted to busy low delay t 30 50 ns refer to figures 15 and 16 (slave serial interface modes) 2 external sclk setup time t 31 5ns external sclk active edge to sdout delay t 32 316ns sdin setup time t 33 5ns sdin hold time t 34 5ns external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns notes 1 in warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time. 2 in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 3 if the polarity of sclk is inverted, the timing references of sclk are also inverted. specifications subject to change without notice. (continued) i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf * * in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. figure 1. load circuit for digital interface timing, sdout, sync, sclk outputs, c l = 10 pf 0.8v 2v 2v 0.8v 0.8v 2v t delay t delay figure 2. voltage reference levels for timing
rev. 0 C5C ad7650 ordering guide model temperature range package description package option ad7650ast C40 c to +85 c quad flatpack (lqfp) st-48 ad7650astrl C40 c to +85 c quad flatpack (lqfp) st-48 AD7650ACP 1 C40 c to +85 c quad flatpack (lfcsp) cp-48 1 AD7650ACPrl 1 C40 c to +85 c quad flatpack (lfcsp) cp-48 1 eval-ad7650cb 2 evaluation board eval-control brd2 3 controller board notes 1 future product. contact factory for availability. 2 this board can be used as a standalone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstrati on purposes. 3 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designator. absolute maximum ratings 1 analog inputs in+ 2 , ref, inC, refgnd . . . . . . . . . . . . avdd + 0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . to agnd C 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . . . . . . . . 7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs except the data bus d(7:4) . . . . C0.3 v to dvdd + 0.3 v data bus inputs d(7:4) . . . . . . . C0.3 v to ovdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . 700 mw junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91 c/w, jc = 30 c/w. 48-lead lfcsp: jc = 26 c/w. caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the ad7650 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device
rev. 0 ad7650 C6C pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin 2 avdd p input analog power pins. nominally 5 v. 3, 40C42, nc no connect 44C48 4 dgnd di must be tied to the ground where dvdd is referred. 5 ob/2c di straight binary/binary twos complement. when ob/2c is high, the digital output is straight binary; when low, the msb is inverted resulting in a twos complement output from its internal shift register. 6 warp di mode selection. when high and impulse low, this input selects the fastest mode, the maximum throughput is achievable, and a minimum conversion rate must be applied in order to guarantee full specified accuracy. when low, full accuracy is maintained independent of the minimum conversion rate. 7 impulse di mode selection. when high and warp low, this input selects a reduced power mode. in this mode, the power dissipation is approximately proportional to the sampling rate. 8 ser/ par di serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. 9C12 data[0:3] do bit 0 to bit 3 of the parallel port data output bus. these pins are always outputs, regardless of the state of ser/ par . 13 data[4] di/o when ser/ par is low, this output is used as bit 4 of the parallel port data output bus. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. with ext/ int tied low, the internal clock is selected on sclk output. with ext/ int set to a logic high, output data is synchronized to an external clock signal connected to the sclk input. 14 data[5] di/o when ser/ par is low, this output is used as bit 5 of the parallel port data output bus. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. it is active in both master and slave mode. when low, sync is active high. when high, sync is active low. 15 data[6] di/o when ser/ par is low, this output is used as bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk signal. it is active in both master and slave mode. pin configuration 48-lead lqfp and 48-lead lfscp (st-48 and cp-48) 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd av d d nc dgnd ob/ 2c warp impulse nc = no connect ser/ par d0 d1 d2 busy d15 d14 d13 ad7650 d3 d12 d4/ext/ int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror nc nc nc nc nc in+ nc nc nc in refgnd ref
rev. 0 C7C ad7650 pin function descriptions (continued) pin no. mnemonic type description 16 data[7] di/o when ser/ par is low, this output is used as bit 7 of the parallel port data output bus or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy chain the conversion results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the data is output on sdout during conversion. when rdc/sdin is low, the data can be output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground 18 ovdd p input/output interface digital power. nominally at the same supply than the supply of the host interface (5 v or 3 v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground 21 data[8] do when ser/ par is low, this output is used as bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in an on-chip register. the ad7650 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/2c. in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on sclk falling edge and valid on the next rising edge. 22 data[9] di/o when ser/ par is low, this output is used as the bit 9 of the parallel port data output bus. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 data[10] do when ser/ par is low, this output is used as the bit 10 of the parallel port data output bus. or sync when ser/ par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and remains high while sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. 24 data[11] do when ser/ par is low, this output is used as the bit 11 of the parallel port data output bus. or rderror when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as a incomplete read error flag. in slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25C28 data[12:15] do bit 12 to bit 15 of the parallel port data output bus. these pins are always outputs regardless of the state of ser/ par . 29 busy do busy output. transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock. 33 reset di reset input. when set to a logic high, reset the ad7650. current conversion if any is aborted. if not used, this pin could be tied to dgnd. 34 pd di power-down input. when set to a logic high, power consumption is reduced and conversions are inhibited after the current one is completed.
rev. 0 ad7650 C8C definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 011 . . . 10 to 011 . . . 11 in twos comple- ment coding) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (2.49994278 v for the 0 vC2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level 1/2 lsb above analog ground (19.073 v for the 0 vC2.5 v range). unipolar zero error is the deviation of the actual transition from that point. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/(n+d) by the following formula: enob s n d db =+ [] ? () 176 602 ./. and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic compo- nents to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal to (noise + distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response the time required for the ad7650 to achieve its rated accuracy after a full-scale step function is applied to its input. overvoltage recovery the time required for the adc to recover to full accuracy after an analog input signal 150% of full-scale is reduced to 50% of the full-scale value. notes ai = analog input di = digital input di/o = bidirectional digital do = digital output p = power pin function descriptions (continued) pin no. mnemonic type description 35 cnvst di start conversion. a falling edge on cnvst puts the internal sample/hold into the hold state and initiates a conversion. in impulse mode (impulse high and warp low), if cnvst is held low when the acquisition phase (t 8 ) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 36 agnd p must be tied to analog ground 37 ref ai reference input voltage 38 refgnd ai reference input analog ground 39 inC ai analog input ground 43 in+ ai primary analog input with a range of 0 v to v ref .
rev. 0 C9C ad7650 typical performance characteristics code inl lsb 4 3 4 0 16384 65536 32768 49152 0 1 2 3 2 1 tpc 1. integral nonlinearity vs. code code hexa counts 8001 7ffc 8000 7ffd 7fff 7000 6000 5000 4000 8000 8002 8003 8004 8005 3000 2000 1000 0 7ffe 12 0 00 0 14 850 759 7396 7353 tpc 4. histogram of 16,384 conversions of a dc input at the code center frequency khz thd, harmonics db 60 0 65 70 75 80 85 90 95 100 105 110 115 10 100 1k 110 105 100 95 90 85 80 75 70 65 60 sfdr db sfdr thd 2 nd harmonic 3 rd harmonic 115 tpc 7. thd, harmonics, and sfdr vs. frequency code dnl lsb 3 0 16384 65536 32768 49152 0 1 2 3 2 1 tpc 2. differential nonlinearity vs. code frequency khz amplitude db of full scale 0 0 57 228 114 171 60 80 100 120 20 40 140 160 285 f s = 571ksps f in = 45.01khz snr = 87db thd = 96db sfdr = 98db sinad = 86.5db tpc 5. fft plot sampling rate sps operating current a 100k 0.001 0.1 10k 1k 100 10 1 0.1 0.01 1 10 100 1k 10k 100k 1m avdd, warp/normal dvdd, warp/normal avdd, impulse dvdd, impulse ovdd, all modes tpc 8. operating currents vs. sample rate code hexa counts 10000 8002 7ffd 8001 7ffe 8000 7000 6000 5000 4000 9000 8000 8003 8004 8005 8006 3000 2000 1000 0 0 0 79 151 1 0 0 7fff 3336 3303 9514 tpc 3. histogram of 16,384 conversions of a dc input at the code transition frequency khz snr and s/[n+d] db 100 110 1k 100 85 80 75 70 95 90 enob snr sinad 15.0 14.5 14.0 13.5 13.0 12.5 12.0 enob bits tpc 6. snr, s/(n+d), and enob vs. frequency 50 0 t 12 delay ns c l pf 200 50 20 10 0 100 150 30 40 ovdd = 2.7v, 85 c ovdd = 2.7v, 25 c ovdd = 5v, 85 c ovdd = 5v, 25 c tpc 9. typical delay vs. load capacitance c l
rev. 0 ad7650 C10C circuit information the ad7650 is a very fast, low power, single supply, precise 16-bit analog-to-digital converter (adc). the ad7650 features different modes to optimize performances according to the applications. in warp mode, the ad7650 is capable of converting 570,000 samples per second (570 ksps). the ad7650 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. the ad7650 can be operated from a single 5 v supply and be interfaced to either 5 v or 3 v digital logic. it is housed in 48-lead lqfp or in a tiny 48-lfcsp packages that save space and allows flexible configurations as either serial or parallel interface. the ad7650 is pin-to-pin compatible with the ad7664. converter operation the ad7650 is a successive-approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the capacitive dac con sists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparators negative input is connected to a dummy capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparators positive input is connected to agnd via sw a . all independent switches are connected to the analog input in+. thus, the capacitor array is used as a sampling capacitor and acquires the analog signal on in+ input. similarly, the dummy capacitor acquires the analog signal on inC input. when the cnvst input goes low, a conversion phase is initiated. when the conversion phase begins, sw a and sw b are opened first. the capacitor array and the dummy capacitor are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between in+ and inC captured at the end of the acquisition phase is applied to the comparator inputs, causing the comparator to become unbal- anced. by switching each element of the capacitor array between refgnd or ref, the comparator input varies by binary- weighted voltage steps (v ref /2, v ref /4,...v ref /65536). the control logic toggles these switches, starting with the msb first, to bring the comparator back into a balanced condition. after the completion of this process, the control logic generates the adc output code and brings busy output low. modes of operation the ad7650 features three modes of operations, warp, normal, and impulse. each of these modes is more suitable for specific applications. the warp mode allows the fastest conversion rate up to 570 ksps. however, in this mode, and this mode only, the full specified accuracy is guaranteed only when the time between conversion does not exceed 1 ms. if the time between two consecutive conversions is longer than 1 ms, for instance, after power-up, the first conversion result should be ignored. this mode makes the ad7650 ideal for applications where both high accuracy and fast sample rate are required. the normal mode is the fastest mode (500 ksps) without any limitation about the time between conversions. this mode makes the ad7650 ideal for asynchronous applications such as data acqui- sition systems, where both high accuracy and fast sample rate are required. it is selected when both impulse and warp are low. the impulse mode, the lowest power dissipation mode, allows power saving between conversions. when operating at 100 sps, for example, it typically consumes only 21 w. this feature makes the ad7650 ideal for battery-powered applications. sw a comp sw b in+ ref refgnd lsb msb 32,768c in 16,384c 4c 2c c c 65,536c control logic switches control busy output code cnvst figure 3. adc simplified schematic
rev. 0 C11C ad7650 transfer functions using the ob/ 2c digital input, the ad7650 offers two output codings: straight binary and twos complement. the lsb size is v ref /65536, which is about 38.15 v. the ideal transfer char- acteristic for the ad7650 is shown in figure 4 and table i. 000...000 000...001 000...010 111...101 111...110 111...111 adc code straight binary analog input v ref 1.5 lsb v ref 1 lsb 1 lsb 0v 0.5 lsb 1 lsb = v ref /65536 figure 4. adc ideal transfer function table i. output codes and ideal input voltages digital output code (hex) analog straight two? description input binary complement fsr C 1 lsb 2.499962 v ffff 1 7fff 1 fsr C 2 lsb 2.499923 v fffe 7ffe midscale + 1 lsb 1.250038 v 8001 0001 midscale 1.25 v 8000 0000 midscale C 1 lsb 1.249962 v 7fff ffff Cfsr + 1 lsb 38 v 0001 8001 Cfsr 0 v 0000 2 8000 2 notes 1 this is also the code for overrange analog input (v in+ C v inC above v ref C v refgnd ). 2 this is also the code for underrange analog input (v in+ below v inC ). notes 1. the adr421 is recommended with c ref = 47 f. 2. the ad8021 is recommended with a compensation capacitor c c = 10pf, type ceramic npo. 3. optional low jitter cnvst . ad7650 2.5v ref note 1 note 2 u1 d note 3 clock c/ p/dsp serial port digital supply (3.3v or 5v) dvdd 100nf + 10 f 100nf + 10 f 100 100nf + 10 f analog supply (5v) + c ref 1 1 f 4.7nf c c 15 analog input (0v to 2.5v) pd reset cs rd impulse warp ser/ par ob/ 2c cnvst busy sdout sclk in in+ refgnd ref agnd avdd dgnd dvdd ovdd ognd figure 5. typical connection diagram typical connection diagram figure 5 shows a typical connection diagram for the ad7650.
rev. 0 ad7650 C12C ? the noise generated by the driver amplifier needs to be kept as low as possible to preserve the snr and transition noise performance of the ad7650. the noise coming from the driver is filtered by the ad7650 analog input circuit one-pole low-pass filter made by r1 and c2 or the external filter if any are used. ? the driver needs to have a thd performance suitable to that of the ad7650. the ad8021 meets these requirements and is usually appropri- ate for almost all applications. the ad8021 needs an external compensation capacitor of 10 pf. this capacitor should have good linearity as an npo ceramic or mica type. the ad8022 could also be used where dual version is needed and gain of 1 is used. the ad829 is another alternative where high-frequency (above 100 khz) performance is not required. in gain of 1, it requires an 82 pf compensation capacitor. the ad8610 is another option where low bias current is needed in low-frequency applications. voltage reference input the ad7650 uses an external 2.5 v voltage reference. the volt- age reference input ref of the ad7650 has a dynamic input impedance. therefore, it should be driven by a low impedance source with an efficient decoupling between ref and refgnd inputs. this decoupling depends on the choice of the voltage reference, but usually consists of a low esr tantalum capacitor connected to the ref and refgnd inputs with minimum para- sitic inductance. 47 f is an appropriate value for tantalum capacitor when used with one of the recommended reference voltages: ? the low-noise, low temperature drift adr421 and ad780 voltage references. ? the low-power adr291 voltage reference. ? the low-cost ad1582 voltage reference. for applications using multiple ad7650s, it is more effective to buffer the reference voltage with a low-noise, very stable op amp such as the ad8031. care should also be taken with the reference temperature coeffi- cient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/ c tempco of the reference changes the full scale by 1 lsb/ c. note that v ref , as mentioned in the specification table, could be increased to avdd C1.85 v. since the input range is defined in terms of v ref , this would essentially increase the range to make it a 0 v to 3 v input range with a reference voltage of 3 v. the ad780 can be selected with a 3 v reference voltage. power supply the ad7650 uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply as shown in figure 5. the ad7650 is independent of power supply sequencing and thus free from supply voltage induced latchup. analog input figure 6 shows an equivalent circuit of the input structure of the ad7650. c2 r1 d1 d2 c1 in+ or in agnd av d d figure 6. equivalent analog input circuit the two diodes, d1 and d2, provide esd protection for the analog inputs in+ and inC. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v. this will cause these diodes to become forward-biased and start conducting current. these diodes can handle a forward- biased current of 100 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from avdd. in such case, an input buffer with a short circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differential signal between in+ and inC. unlike other converters, the inC input is sampled at the same time as the in+ input. by using this differential input, small signals common to both inputs are rejected. for instance, by using inC to sense a remote signal ground, difference of ground potentials between the sensor and the local adc ground are eliminated. during the acquisition phase, the impedance of the analog input in+ can be modeled as a parallel combination of capacitor c1 and the network formed by the series connection of r1 and c2. capacitor c1 is primarily the pin capacitance. the resistor r1 is typically 140 ? and is a lumped component made up of some serial resistors and the on resistance of the switches. the capacitor c2 is typically 60 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c1. the r1, c2 makes a one- pole low-pass filter that reduces undesirable aliasing effect and limits the noise. when the source impedance of the driving circuit is low, the ad7650 can be driven directly. large source impedances will significantly affect the ac performances, especially the total harmonic distortion. driver amplifier choice although the ad7650 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? the driver amplifier and the ad7650 analog input circuit must be able together to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). in the amplifiers data sheet, the settling at 0.1% to 0.01% is more commonly specified. it could significantly differ from the settling time at 16-bit level and it should therefore be verified prior to the driver selection. the tiny op amp ad8021, which combines ultralow noise and a high-gain bandwidth, meets this settling time requirement even when used with high gain up to 13.
rev. 0 C13C ad7650 power dissipation vs. throughput operating currents are very low during the acquisition phase, which allows a significant power saving when the conversion rate is reduced as shown in figure 7. this power saving depends on the mode used. in impulse mode, the ad7650 automatically reduces its power consumption at the end of each conversion phase. this feature makes the ad7650 ideal for very low power battery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power supply rails (i.e., dvdd or dgnd for all inputs except ext/ int , invsync, invsclk, rdc/sdin, and ovdd or ognd for these last four inputs). 100k 0.1 power dissipation w sampling rate sps 100k 1k 10 1 100 10k 1m 10k 1k 100 10 1 0.1 warp/normal impulse figure 7. power dissipation vs. sampling rate conversion control figure 8 shows the detailed timing diagrams of the conversion process. the ad7650 is controlled by the signal cnvst which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conver- sion is complete. the cnvst signal operates independently of cs and rd signals. cnvst busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acquire convert acquire convert figure 8. basic conversion timing in impulse mode, conversions can be automatically initiated. if cnvst is held low when busy is low, the ad7650 controls the acquisition phase and then automatically initiates a new conversion. by keeping cnvst low, the ad7650 keeps the conversion process running by itself. it should be noted that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the ad7650 could sometimes run slightly faster then the guaranteed limits in the impulse mode of 444 ksps. this feature does not exist in warp or normal m odes. t 9 t 8 reset data busy cnvst figure 9. reset timing although cnvst is a digital signal, it should be designed with special care with fast, clean edges, and levels with minimum overshoot and undershoot or ringing. it is a good thing to shield the cnvst trace with ground and also to add a low value serial resistor (i.e., 50 v) termination close to the output of the component that drives this line. for applications where the snr is critical, cnvst signal should have a very low jitter. some solutions to achieve that is to use a dedicated oscillator for cnvst generation or, at least, to clock it with a high-frequency low-jitter clock as shown in figure 5. digital interface the ad7650 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the ad7650 digital interface also accommodates both 3 v or 5 v logic by simply connecting the ovdd supply pin of the ad7650 to the host system interface digital supply. finally, by using the ob/ 2c input pin, both twos complement or straight binary coding can be used. the two signals cs and rd control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each ad7650 in multicircuits applications and is held low in a single ad7650 design. rd is generally used to enable the conversion result on the data bus. t 1 t 3 t 4 t 11 cnvst busy data bus cs = rd = 0 t 10 previous conversion data new data figure 10. master parallel data timing for reading (continuous read)
rev. 0 ad7650 C14C previous conversion t 1 t 3 t 12 t 13 t 4 cs = 0 cnvst , rd busy data bus figure 12. slave parallel data timing for reading (read during convert) serial interface the ad7650 is configured to use the serial interface when the ser/ par is held high. the ad7650 outputs 16 bits of data, msb first, on the sdout pin. this data is synchronized with the 16 clock pulses provided on sclk pin. the output data is valid on both the rising and falling edge of the data clock. master serial interface internal clock the ad7650 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the ad7650 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. depending on rdc/sdin input, the data can be read after each conversion or during the following conversion. figure 13 and figure 14 show the detailed timing diagrams of these two modes. parallel interface the ad7650 is configured to use the parallel interface when the ser/ par is held low. the data can be read either after each conversion, which is during the next acquisition phase, or dur- ing the following conversion as shown, respectively, in figure 11 and figure 12. when the data is read during the conversion, however, it is recommended that it is read only during the first half of the conversion phase. that avoids any potential feed- through between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion busy data bus cs rd t 12 t 13 figure 11. slave parallel data timing for reading (read after convert) t 3 busy cs , rd cnvst sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 123 141516 d15 d14 d2 d1 d0 x ext/ int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 figure 13. master serial data timing for reading (read after convert)
rev. 0 C15C ad7650 ext/ int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 141516 t 18 busy cs , rd cnvst sync sclk sdout figure 14. master serial data timing for reading (read previous conversion during convert) usually, because the ad7650 is used with a fast throughput, the mode master, read during conversion is the most recommended serial mode when it can be used. in read-during-conversion mode, the serial clock and data toggle at appropriate instants which minimize potential feedthrough between digital activity and the critical conversion decisions. in read-after-conversion mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer busy width. slave serial interface external clock the ad7650 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. the external serial clock is gated by cs . when cs and rd are both low, the data can be read after each conversion or during the following conversion. the external clock can be either a continuous or discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figure 15 and figure 16 show the detailed timing diagrams of these methods. while the ad7650 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. this is par- ticularly important during the second half of the conversion phase because the ad7650 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recom- mended that when an external clock is being provided, it is a discontinuous clock that is toggling only when busy is low or, more importantly, that it does not transition during the latter half of busy high. external discontinuous clock data read after conversion though the maximum throughput cannot be achieved using this mode, it is the most recommended of the serial slave modes. figure 15 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the result of this conversion can be read while both cs and rd are low. the data is shifted out, msb first, with 16 clock pulses and is valid on both rising and falling edge of the clock. among the advantages of this method, the conversion perfor- mance is not degraded because there are no voltage transients on the digital interface during the conversion process. another advantage is to be able to read the data at any speed up to 40 mhz, which accommodates both slow digital host inter- face and the fastest serial reading. finally, in this mode only, the ad7650 provides a daisy-chain feature using the rdc/sdin input pin for cascading multiple converters together. this feature is useful for reducing compo nent count and wiring connections when desired as, for instance, in isolated multiconverter applications. an example of the concatenation of two devices is shown in figure 17. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the edge of sclk opposite to the one used to shift out the data on sdout. hence, the msb of the upstream converter just follows the lsb of the downstream converter on the next sclk cycle.
rev. 0 ad7650 C16C sclk sdout d15 d14 d1 d0 d13 x15 x14 x13 x1 x0 y15 y14 cs busy sdin ext/ int = 1 invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 x15 x14 x 1 2 3 14151617 18 rd = 0 t 34 figure 15. slave serial data timing for reading (read after convert) sdout cs sclk d1 d0 x d15 d14 d13 123 141516 t 3 t 35 t 36 t 37 t 31 t 32 t 16 cnvst busy ext/ int = 1 invsclk = 0 rd = 0 figure 16. slave serial data timing for reading (read previous conversion during convert) sclk sdout rdc/sdin busy busy data out ad7650 #1 (downstream) busy out cnvst cs sclk ad7650 #2 (upstream) rdc/sdin sdout sclk in cs in cnvst in cnvst cs figure 17. two ad7650s in a daisy-chain configuration external clock data read during conversion figure 16 shows the detailed timing diagrams of this method. during a conversion, while both cs and rd are both low, the result of the previous conversion can be read. the data is shifted out, msb first, with 16 clock pulses and is valid on both rising and falling edge of the clock. the 16 bits have to be read before the current conversion is complete. if that is not done, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy chain feature in this mode and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock of, at least 18 mhz, when impulse mode is used, 25 mhz when normal mode is used or 40 mhz when warp mode is used, is recommended to ensure that all the bits are read during the first half of the conversion phase. it is also possible to begin to read the data after conversion and continue to read the last bits even after a new conversion has been initi ated. that allows the use of a slower clock speed like 14 mhz in im pulse mode, 18 mhz in normal mode and 25 mhz in warp mode.
rev. 0 C17C ad7650 microprocessor interfacing the ad7650 is ideally suited for traditional dc measurement appli- cations supporting a microprocessor, and ac signal processing applications interfacing to a digital signal processor. the ad7650 is designed to interface either with a parallel 16-bit-wide interface or with a general-purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the ad7650 to prevent digital noise from coupling into the adc. the following sections illustrate the use of the ad7650 with an spi-equipped microcontroller, the adsp-21065l and adsp-218x signal processors. spi interface (mc68hc11) figure 18 shows an interface diagram between the ad7650 and an spi-equipped microcontroller like the mc68hc11. to accom- modate the slower speed of the microcontroller, the ad7650 acts as a slave device and data must be read after conversion. this mode allows also the daisy chain feature. the convert command could be initiated in response to an internal timer interrupt. the reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conver sion signal (busy going low) using to an interrupt line of the micro controller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr = 1), clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1 and spi interrupt enable (spie = 1) by writing to the spi control reg- ister (spcr). the irq is configured for edge-sensitive-only operation (irqe = 1 in option register). irq mc68hc11 * cnvst ad7650 * cs busy miso/sdi sck i/o port sdout sclk rd invsclk ext/ int ser/ par dvdd * additional pins omitted for clarity ovdd figure 18. interfacing the ad7650 to spi interface adsp-21065l in master serial interface as shown in figure 19, the ad7650 can be interfaced to the adsp-21065l using the serial interface in master mode without any glue logic required. this mode combines the advantages of reducing the number of wire connections and being able to read the data during or after conversion at user convenience. the ad7650 is configured for the internal clock mode (ext/ int low) and acts, therefore, as the master device. the convert com- mand can be generated by either an external low jitter oscillator or, as shown, by a flag output of the adsp-21065l or by a frame output tfs of one serial port of the adsp-21065l which can be used as a timer. the serial port on the adsp-21065l is configured for external clock (irfs = 0), rising edge active (ckre = 1), external late framed sync signals (irfs = 0, lafs = 1, rfsr = 1) and active high (lrfs = 0). the serial port of the adsp-21065l is configured by writing to its receive control register (srctl)see adsp-2106x sharc users manual. because the serial port within the adsp-21065l will be seeing a discontinuous clock, an initial word reading has to be done after the adsp-21065l has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. rfs adsp-21065l * sharc cnvst ad7650 * cs sync rd dr rclk flag or tfs sdout sclk invsync invsclk ext/ int rdc/sdin ser/ par dvdd * additional pins omitted for clarity ovdd or ognd figure 19. interfacing to the adsp-21065l using the serial master mode
rev. 0 ad7650 C18C application hints bipolar and wider input ranges in some applications, it is desired to use a bipolar or wider ana- log input range like, for instance, 10 v, 5 v or 0 v to 5 v. although the ad7650 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. figure 20 shows a connection diagram which allows that. compo- nents values required and resulting full-scale ranges are shown in table ii. u1 2.5v ref analog input r2 r3 r4 100nf r1 u2 c ref in+ in ref refgnd 1mf ad7650 5v 10nf figure 20. using the ad7650 in 16-bit bipolar and/or wider input ranges table ii. component values and input ranges input range r1 r2 r3 r4 10 v 250 ? 2 k ? 10 k ? 8 k ? 5 v 500 ? 2 k ? 10 k ? 6.67 k ? 0 v to C5 v 1 k ? 2 k ? none 0 ? for applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer, u2, as shown for bipolar input ranges in figure 20. layout the ad7650 has very good immunity to noise on the power supplies as can be seen in figure 9. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the ad7650 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the ad7650 or, at least, as close as possible to the ad7650. if the ad7650 is in a system where multiple devices require analog-to-digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the ad7650. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the ad7650 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sec- tions of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supplies lines to the ad7650 should use as large trace as possible to provide low impedance paths and reduce the effect of glitches on the power supplies lines. good decoupling is also important to lower the supplies impedance presented to the ad7650 and reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supplies pins avdd, dvdd, and ovdd close to, and ideally right up against, these pins and their correspond- ing ground pins. additionally, low esr 10 f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the dvdd supply of the ad7650 can either be a separate supply or come from the analog supply avdd or the digital interface supply ovdd. when the system digital supply is noisy, or fast switching digital signals are present, it is recommended that if no separate supply is available, connect the dvdd digital supply to the analog supply, avdd, through an rc filter as shown in figure 5, and connect the system supply to the inter- face digital supply, ovdd, and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. the ad7650 has five different ground pins: inC, refgnd, agnd, dgnd, and ognd. inC is used to sense the analog input signal. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. this ground must be connected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depending on the configuration. ognd is connected to the digital system ground. evaluating the ad7650 performance a recommended layout for the ad7650 is outlined in the evaluation board for the ad7650. the evaluation board package includes a fully assembled and tested evaluation board, documen tation, and software for controlling the board from a pc via the eval-control board.
rev. 0 C19C ad7650 outline dimensions dimensions shown in inches and (mm). 48-lead quad flatpack (lqfp) (st-48) seating plane 0.006 (0.15) 0.002 (0.05) top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.2) 0.004 (0.09) 08 min coplanarity 0.003 (0.08) 7 0 0.057 (1.45) 0.053 (1.35) controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design 48-lead frame chip scale flatpack (lfcsp) (cp-48) pin 1 indicator top view 0.266 (6.75) bsc sq 0.276 (7.0) bsc sq 1 48 1 2 13 37 36 24 25 bottom view 0.215 (5.45) 0.209 (5.30) sq 0.203 (5.15) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.024 (0.60) 0.017 (0.42) 0.009 (0.24) 0.020 (0.50) 0.016 (0.40) 0.012 (0.30) 0.012 (0.30) 0.009 (0.23) 0.007 (0.18) 0.020 (0.50) bsc 0.031 (0.80) max 0.026 (0.65) nom 128 max 0.039 (1.00) max 0.033 (0.85) nom 0.008 (0.20) ref 0.002 (0.05) 0.0004 (0.01) 0.0 (0.0) paddle connected to agnd controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design
C20C c02770C0C1/02(0) printed in u.s.a.

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